We are looking at moving some code into a CPLD or FPGA in order to make it faster. I have worked with Xilinks and their suite of tools before, but for some reason it was decided that we'd use Altera this time around so I am trying to get used to Quartus II.
In particular, I am looking for a way to explicityly assign pins to the chip I am using. In Xilinx, I'd edit the netlist file but I can find no such thing in Quartus. There is a program (Assignments => Pin Planner) that does this, but it has a clunky GUI and I'd far prefer to edit the pins in a text editor, so my twofold question is
A: How do I find the file that stores the pin assignment? It's not listed under my files in the project navigator but the pins I've assigned in Pin Planner stay from session to session so they must be stored somewhere.
B: Is this a horrible idea?
IDE is Quartus II 10.1 Development kit is MAX II Development Board Language is VHDL
EDIT: Right now, I've run into the problem that I'm trying to interface with the Dev Kit through USB. I'm making a serial data receiver on it and have given it a Data In pin. The Dev Kit has a USB receiver so I'm trying to map din to whichever pin the USB connector is on. According to a file I have (rm_maxII-develop_board-rev1.pdf) the USB connector is on "Board Designation U13" but when I go into the Pin PLanner and try to assign that, there is no PIN_U13. I suspect this is an error in the pdf, rather than in Pin Planner but seing as I've never worked with Altera products before, I'm very confused.
chip_pin VHDL Synthesis Attribute
A VHDL synthesis attribute that assigns device pins to a port on a VHDL entity.
To use the synthesis attribute in a , declare the synthesis attribute using an Attribute Declaration, and then set the value of the synthesis attribute on an entity port using an Attribute Specification that you place in the entity's underlying architecture. The value of the synthesis attribute must be a literal containing a list of device pin names separated by commas ().
You can use the synthesis attribute only on entity ports with single-bit or one-dimensional types. For one-dimensional ports, the port's range declaration determines the mapping of pins listed in the synthesis attribute to individual bits in the port. For example, in the following code, the synthesis attribute assigns device pins to ports and on entity :entity foo is port (sel : in std_logic; data : in std_logic_vector(3 downto 0); o : out std_logic); end foo; architecture rtl of foo is attribute chip_pin : string; attribute chip_pin of sel : signal is "C4"; attribute chip_pin of data : signal is "D1, D2, D3, D4"; begin -- Specify additional code end architecture;
In this example, is a one bit wide port; pin is assigned to this port. is a one-dimensional port that is four bits wide. Because is declared with type , pin is assigned to , pin is assigned to , and so forth. If you declared with type , pin would be assigned to , pin would assigned to , and so forth.
Note: The number of entries in the synthesis attribute's comma-delimited list must match the number of bits in the port. To leave a specific bit in a one-dimensional port unassigned, leave its corresponding pin assignment blank.
You cannot use the synthesis attribute to make pin assignments on non-entity ports or ports with more than two dimensions.